DB003-110926-EVB001


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GreenArrays

Produ
ct Data Book DB003
Revised

9/26/11



Evaluation Board
Reference Manual

for EVB001 rev 0.1.1
with G144A12 chips
The GreenArrays EVB001 Evaluation Board is a versatile and powerful application development
platform for the GA144-1.20 chips. As such it has many configuration options.
The current Printed
Circuit Board (PCB) revision shown on the silkscreen is 0.1.1, and it is currently shipped with a starter
eForth that may be booted from flash.
Please familiarize yourself with this information before using the Eval Board so that you will be aware
of the many configuration options available to you.
In addition, please download and read the other relevant documentation such as the Programmers'
Reference for the F18 computers (DB001), the G144A12 Chip Data Book (DB002), and the User's
Manuals for arrayForth
, eForth, polyFORTH®, and other Application Notes as appropriate. The
current editions of all GreenArrays documents, including this one, may be found on our website at
http://www.greenarraychips.com
.
It is always advisable to ensure that you are using the latest

documents before starting work.

��DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
2

Contents
Introduction
..............................................................................
4
Related Documents
..........................................................................................
4
Status of Data Given
........................................................................................
4
Documentation Conventions
............................................................................
4
Numbers
..............................................................................................................
4
Node coordinates
................................................................................................
. 4
Register names
.....................................................................................................
4
Bit Numbering
......................................................................................................
4
Basic Architecture
......................................................................
5
Highlights
........................................................................................................
5
Simplified Block Diagram
.................................................................................
6
Header Orientation
..........................................................................................
6
Board Floorplan
...............................................................................................
7
Software Support
.............................................................................................
7
Power Configuration
..................................................................
8
ain 1.8v Bus
..................................................................................................
8
xternal DC Supplies
........................................................................................
8
Power Selection and Measurement
................................................................
. 8
Other Available Voltages
.................................................................................
8
USB Interfaces
...........................................................................
9
Interface Devices
.............................................................................................
9
Jumpers and Connections
................................................................................
9
Flash Configuration
.........................................................................................
9
Host Chip
.................................................................................
�� DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
3

Target Chip
.............................................................................
��DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
4

Introduction
This is the primary reference manual for the EVB001 Evaluation Board. With two GreenArrays G144A12 chips,
peripherals sufficient for a complete software and hardware development environment, and a large prototyping area,
this highly configurable board is intended to serve both engineers and programmers well in evaluating our chips in all
stages of application development.
Initially shipped with eForth in flash, this board is field upgradable with additional system software, such as
polyFORTH
In addition, our Application Notes will use this board as their default platform so that our customers may
make immediate use of the hardware and software solutions published in those exercises.
1.1
Related Documents
This book describes an application of GreenArray chips, in particular the GA144. In the interest of avoiding needless
and often confusing redundancy, it is designed to be used in combination with other documents.
The general characteristics and programming details for the F18A computers and I/O used in the GA144 are described
in a separate document; please refer to
F18A Technology Reference
The boot protocols supported by the chip are
detailed in
Boot Protocols for GreenArrays Chips
The configuration and electrical characteristics of the chip are
documented in
G144A12 Chip Reference.
The current editions of these, along with many other relevant documents
and application notes as well as the current edition of this document, may be found on our website at
http://www.greenarraychips.com
. It is always advisable to ensure that you are using the latest documents before
starting work.
1.2
Status of Data Given
The data given herein are
Production,
reflecting board revision 0.1.1.
1.3
Document
ation Conventions
1.3.1
Numbers
Numbers are written in decimal unless otherwise indicated. Hexadecimal values are indicated by explicitly writing
“hex” or by preceding the number with the lowercase letter “x”. Ln colorCorth coding examples, hexadecimal values
are italicized and darkened.
1.3.2
Node coordinates
Each GreenArrays chip is a rectangular array of
each of which is an F18 computer. By convention these arrays
are represented as seen from the top of the silicon die, which is normally the top of the chip package, oriented such
that pin 1 is in the upper left corner. Within the array, each node is identified by a three or four digit number denoting
its Cartesian coordinates within the array as
or
with the lower left corner node always being designated as
node 000. Thus, for a GA144 chip whose computers are configured in an array of 18 columns and 8 rows, the numbers
of the nodes in the lower right, upper left, and upper right corners are 017, 700, and 717 respectively.
1.3.3
Register names
Register names in prose may be used with or without the word "register" and are usually shown in a bold font and
capitalized where necessary to avoid ambiguity, such as for example the registers
T S R I A B
and
or
.
1.3.4
Bit Numbering
Binary numbers are represented as a horizontal row of bits, numbered consecutively right to left in ascending
significance with the least significant bit numbered zero. Thus bit
has the binary value 2
. The notation P9 means bit
9 of register
, whose binary value is x200, and T17 means the sign (high order) bit of 18-bit register
.
�� DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
5

Basic
Architecture
The purpose of this board is to facilitate evaluation and application prototyping using GreenArrays chips. Because no
single I/O complement would be suitable for all likely uses, this board has two GA144 chips: One (called "Host")
configured with sufficient I/O for intensive software development, and the other (called "Target") with as little I/O
committed as possible so that pure, dedicated applications may be prototyped.
2.1
Highlights
Three FTDI USB to serial chips provide high speed (960 kBaud) communications for interactive software development
and general-purpose host communications.
An onboard switching regulator takes power from the USB connectors and/or a conventional "wall wart" power supply.
Whichever of these is offering the highest voltage is used by the regulator.
A barrier strip provides for connection of bench power supplies
Each of the power buses of the two GA144 chips may
selectively be run from external power in lieu of the onboard regulator, allowing you to run either chip from any
desired V
voltage and also facilitating current measurements.
The Host chip is supplied with an SPI boot flash holding 1 MByte of nonvolatile data, an external SRAM with 1 MWord
(2 MBytes) of memory; and may optionally use a dual voltage MMC card such as the 2 Gigabyte unit we have selected
for in-house use. These memory resources may be used in conjunction with Virtual Machines such as eForth and
polyFORTH, or for direct use by your own F18 code.
The Target chip is committed to as few I/O connections as possible. The sources for its reset signal are fully
configurable, and with the exception of a SERDES line connecting it with the Host chip, all other communications (two
2-wire serial interfaces) may be disconnected so that the chip is fully isolated and thus all practical I/O is available for
any desired use.
Roughly half the board is prototyping area, mainly populated with a grid of plated through holes on 0.1 inch centers.
By soldering suitable headers to this grid, you can provide for expansion using various prototyping fixtures such as

��DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
6

2.2
Simplified
Block Diagram
2.3
Header Orientation
For all single-row headers or hole patterns, pin 1 is at the left as viewed from the top side of the board with USB
connectors in the upper left corner; for single column patterns, pin 1 is at the top. For headers with 2 pin short
dimensions, pin 1 will be in the lower left corner for horizontally oriented patterns and in the upper left corner for
vertical patterns. In the special case of 2x2 patterns, pin 1 is always in the upper left corner. The following diagrams
illustrate these orientation conventions and pin numbering:
1

2

3


1


2

4

6


1

2


1

2





2


1

3

5


3

4


3

4





3






5

6








As delivered, Host chip boots a Virtual Machine such as eForth or polyFORTH from
flash and talks to terminal on RS232 port B. Ports A and C are available for IDE
operations on Host and Target chips. Target may be fully isolated from Host with the
exception of the SERDES connection. Other software options including other Virtual
Machines besides eForth will be available for field upgrade.
GA144
1
1 M
(VM)
GA144
0
300.1/17
2 M
(VM)
WITCHING
300.1/17
001.
1/17
701.
1/17
200.17
100.17
B
A
C
708.1/17
708.1/17
500.17
0
PTIONAL
1.8
2GB
�� DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
7

2.4
Board Floorplan
This overhead image of the evaluation board shows the spatial relationships among the subdivisions that are discussed
in the following sections.
2.5
Software Support
This board is supported by four major classes of software:
arrayForth
is presently the principal tool for creation of native code, or microcode, to run directly on the F18
computers in our chips. Included are compilers, simulators, an Interactive Development Environment (IDE),
and boot stream generator. arrayForth maintains F18 source code in
colorForth
notation.
The arrayForth
system itself is written in and runs on colorForth, which may be run on a wide variety of platforms.
Virtual Machines
running in clusters of F18 nodes support high level programming environments whose
natures imply external memory resources. Examples are
eForth
and
polyFORTH
These environments may
interact with microcode running in the rest of the chip, supervising their high performance activities. Some
environments may also support development of native F18 code as a supplement or complement to
arrayForth.
Host platform
plications
, such as enhanced terminal emulators, may be supplied with the virtual machines
or other applications that use them.
Applications provided for this board
will include source code for arrayForth and/or for specific Virtual
Machines, and often hardware configuration or modification instructions, as appropriate.
Software options for GreenArrays chips and boards are continually being developed, and may be obtained from our
website.

��DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
8

Power Configuration
You must ensure there is enough power for the intended use of the
board. Minimal USB (80% of 440 mW) is sufficient for eForth or
polyFORTH and many typical projects, but power requirements can
exceed 400 mW for V
C (core power) if enough F18A computers are
busy simultaneously, and likewise V
I (I/O power) can be greater than this depending on what you connect to the
chips.
Several power sources are available in the upper left corner of the board.
3.1
Main 1.8v Bus
Primary 1.8v power is supplied by an onboard fixed voltage regulator fed by an optional
“wall wart”
(type N plug,
positive center conductor, voltage
at the J2 connector
3.6 to 19.5VDC with recommended minimum of 4.0V
and up to
three USB connectors. Each source is diode protected from the others so whichever one is supplying the highest
voltage will be the one that is used at any given time; these diodes have an internal drop of 200 to 300 mV. Each USB
connector communicates with a USB host using an FTDI chip. The power available from each USB connection varies
from a minimum of 100 mA at 4.4V to the maximum of 500 mA at 5V; the FTDI chips are configured to request
permission to use the maximum to improve flexibility. An efficient (
78%) switching regulator produces a maximum of
2A at 1.8V for the logic circuitry on the board.
If this full rated power is needed, a "wall wart" capable of delivering 4.5
to 5 watts will be required (efficiency varies with voltage.)
The main 1.8v bus is used to power our side of the FTDI chips, the SPI flash, the Host chip's external SRAM, and the two
logic chips used in SPI bus multiplexing. This bus is also the default source of V
C, V
I and V
A for the Host and
Header

Chip

Bus

Pins 1
-
2 connected

Pins 2
-
3 connected

J
10

Host

V
DD
C

J1 pin 3

Main 1.8v Bus

J11

V
DD
I/A

J14

Target

V
DD
C

J1 pin 1

J15

V
DD
I

J16

V
DD
A

Current may be measured by inserting a shunt or other type ammeter across the desired pair of pins. Some
combinations of current and shunt resistance will require use of an adjustable external power supply to give the
desired voltage on the chip side of the shunt.
The jumpers provided are rated at 3A with max resistance of 20 m
.
3.4
Other Available Voltages
An unregulated V
is input to the onboard switching regulator. No contact is provided because the voltage is not
controlled. Each FTDI chip that is connected to a USB host can provide up to 50 mA of 3.3v, made available on J7, J12
and J19 for ports A, B and C respectively.



�� DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
9

USB Interfaces
Three USB device interfaces provide for high speed communications with the GA144 chips. To a host computer each of
these normally appears as an asynchronous serial (COM) port. Although each has a specific planned use on this board,
their configuration is highly flexible.
4.1
Interface Devices
The devices provided are FT232R chips made by Future Technology Devices International, Ltd. (FTDI). As USB to serial
UART devices, their USB side is powered by V
from the USB host while the side which talks to our chips is powered by
the main 1.8v bus regulated on the board. Because the FTDI chips communicate with the GA144s directly using 1.8v
CMOS, signals are crisp enough that each interface can run at an effective speed of 921,600 bau
4.2
Jumpers and
Connections
Transmit and receive lines are routed to the Host and Target GA144 chips as
described in later sections. Request to Send (RTS) signals from ports A and C
are available for chip reset purposes. RTS from port B is available at plated
through hole J24.
Each FTDI chip is configured to drive transmit and receive activity LEDs
D4, D7, D9
and D
respectively.
The remaining three configurable
outputs, and the DTR signal, are available at hole patterns J8, J13 and J17 for
ports A, B and C respectively. By default two of these outputs are
configured with clock signals that may be used for time base purposes.
Each FTDI chip develops 3.3v for internal use. Plated through holes J7, J12 and J19 provide access to this supply from
ports A, B and C respectively; up to 50 mA may be drawn from each of these for your circuitry if needed.
4.3
Flash Configuration
We configure the FTDI FT232RQ chips before shipping the boards by setting the polarities of TXD, RXD and RTS- lines
correctly and by selecting our default outputs for the five CBUS lines as follows: CBUS0 and 1 are incoming and
outgoing activity LED drivers respectively. CBUS2 and 3 are driven with clock frequencies generated by the FTDI chips.
CBUS4 is also driven with the incoming activity signal as a work-around for one of the rev 0.1.1 board errata.
FTDI
Signal

Signal Location

Definition

Port A

Port B

Port C

CBUS0
-

(LED)

(LED)

(LED)

Driven low to indicate inbound ("TX") line activity.

CBUS1
-

(LED)

(LED)

(LED)

Driven low to indicate
outbound ("RX") line activity.

CBUS2
-

J8.1

J13.1

J17.1

Clock output, 6 MHz.

CBUS3
-

J8.2

J13.2

J17.2

Clock output, 48 MHz.

CBUS4
-

J8.3

J13.3

J17.3

Driven low to indicate inbound ("TX") line activity.

DTR
-

J8.4

J13.4

J17.4

Data terminal ready. Default
state and polarity depend on
driver software and configuration.

The FTDI chips are specially configured for their use on this board. Excellent documentation as well as configuration
utilities and drivers are available from the manufacturer at
http://www.ftdichip.com/
. Template files are included in
the software distribution. Please contact us before changing the configuration of your FTDI chips.

��DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
10

The Host chip, designated chip 0 on some of the design
documentation, is by default configured as a development system
including hardware and software support for a high level language
such as eForth or polyFORTH. The photo to the right shows the
section of the board housing this powerful system including 144 F18
computers, two USB serial ports, 1 Megaword (2 MBytes) of
external SRAM, 8 megabits (1 Mbyte) of bootable SPI flash, and
optional provision for using a dual voltage MMC card as onboard
mass storage. All connections make use of software defined I/O
with minimal or no external circuitry.
For example, U9 and U10 are
included only to facilitate selection of multiple SPI devices.
Most host pins, other than those used to control SRAM, are
available at jumper stakes or hole patterns such as J21 and J27.
Several probe points are provided: WE-, CE-, A00 and D00 show
SRAM timing; SS, SCK, DO and DI show signals at the SPI flash chip.
S1 and S17 may be used,
with great care
, to probe the SERDES connection between Host and Target chips.
5.1
J20 pins

Reset Source

None

User provided inputs on pins
1
or
2

1
-
3

USB port A RTS signal


2
-
4

Host chip reset circuit / button

1
-
3
&
2
-
4

Reset circuit / button or USB port A RTS

5.2
Serial Interfaces
USB port A is intended, by default, to be used for programming of the Host chip using the
arrayForth Interactive Development Environment (IDE). Transmit and receive lines may
be connected to async boot node 708 by insertion of jumpers in J23. Reset from port A
may be connected as shown above.
Port B is primarily intended to be used for a serial
interface to the eForth or polyFORTH system; it too may be connected to nodes 100 and
200 by insertion of jumpers in J23. The mapping in J23 is as follows:
Signal

USB
port

J
23
p
ins

Host
pins

USB
port

J23
p
ins

Host
pins

USB
port

J23
pins

Target
pins

Rx to
chip

A

1

2

708.17

B

5

6

200.17

C

9

10

708.17

Tx
from
chip

3

4

708.1

7

8

100.17

11

12

708.1



J20 Pins

1

2

3

4




�� DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
11

5.3
SPI
and Devices
Node 705 of the host chip is equipped with ROM capable of booting from an external flash memory using the 4-wire
SPI interface. Using jumper options, node 705 may be configured to boot from the onboard flash chip. It may also be
configured to selectively use other SPI devices under control of node 600 and/or external logic you provide. One
J25 pins

J26 pins

Configuration

Don't
Care

IN

Pulls Node 705 pin high. Node 705 does not
attempt boot nor does it drive any of its pins.

Don't
Care

OUT

Node 705 attempts reading flash and if validity
checks pass it processes boot frame(s) from that
device.

1
-
2

Don't
Care

Flash chip is

held in reset; all its pins are at high
impedance so that node 705's pins are available
for other use.

2
-
3

Don't
Care

Flash chip is reset by the
Host chip's reset
circuit/button and, if
both
J20
jumpers are
inserted
, by USB port A RTS.

Evaluation boards are shipped with
high-level virtual machine set to boot from flash. New software is initially loaded
into flash using the arrayForth IDE; the procedure for doing this requires use of J26.
For other uses of the flash by software packages such as eForth and polyFORTH, and for software installation
procedures, see the documentation for each software package..
For low-level application use, see arrayForth source code and application notes.
5.3.2
Card Mass Storage
J39 pins

J37 pins

Configuration

2
-
3

1
-
2, 3
-
4

SPI Flash is

always selected. Node 600 unused.

1
-
2

1
-
2, 3
-
4

Node 600 selects SPI flash when its pin is low (reset
condition), or MMC card when the pin is high.


J25

J26

1


2

1

3

2

J39

J37

1

1

2

2

3

4

3





��DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
12

5.3.4
Connecting MMC Power and Signals to SD Socket
The selection logic described in section
drives signals that terminate in J40


�� DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
13

6.

J22

2

4

6

1

3

5




��DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
14

Prototyping Area
Half of the evaluation board's area is available for
your use in building any desired circuitry. We have
made this as flexible as feasible for a broad range of
projects. The area is covered with patterns of plated
through holes to which you may solder components,
connectors, headers and so on as necessary. On the
grounds that it is simpler and easier to solder multi-
pin devices onto a board than it is to remove such
devices when they are in the way, we supply an
assortment of connectors and headers in a separate
bag for your use.
GreenArrays expects to use this evaluation board as
the primary platform for design exercises that will be
published on our website as Application Notes
suggesting ways to make good use of this area.
7.1
Plated
through Hole Grid
The large grid of plated through holes, on 0.1"
centers, gives almost unlimited flexibility i
breadboarding your circuits. The area is compatible
with many common technologies that may be used to attach components, interfaces, or expand the area further by
soldering 0.1" headers to the board in suitable patterns. These options will be expanded upon later.
7.2
Power, Ground and Signals
Hole patterns carrying the main 1.8v bus and common ground are
available surrounding the prototyping area. Other supply voltages
such as 3.3v from the FTDI chips or user supplied voltages from the J1
barrier strip must be hand wired, as must any other signals such as those from GA144 pins.
7.3
Convenience Circuits
For interfacing
devices with signal voltages other than the 1.8v native to the GA144,
there are six 8-bit bidirectional level shifter chips in the prototyping area. These are
Texas Instruments
TXB0108 devices in RGY packages
and for maximum flexibility none
of their pins are connected except ground (pin 11 and die attach paddle.) You may use
each of these chips to interface between 1.2 to 3.6v on the A port and 1.65 to 5.5v on
the B port by connecting suitable supply voltages to each of the chip's two V
pins.
In addition, there are four uncommitted 2-input, 1.8v CMOS logic gates available for your use. These are
located between the Host chip and the hole grid of the prototyping area. The table below identifies the
connections and gate types.
Inputs

Output

Gate Type

TP4

TP5

TP11

2
-
input NAND

TP6

TP7

TP12

TP8

TP9

TP13

TP2

TP3

TP10

2
-
input OR





�� DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
15


7.4
Optional Connec
tor Hole Patterns
Unpopulated hole patterns are provided along the edges of the prototyping area for various connectors. Some
connectors are supplied with the evaluation board so that you may solder in any that you require.
7.4.1
DB9 Connectors
To interface with RS-232 devices, there are two female
DB9 patterns. For your convenience, these are
equipped with minimalist RS232 interfaces that may be
used with our chips: Data receive and RTS signals are
simply connected to GA144 pins through current
limiting resistors, while data transmit is done with a pair
of inverting N transistors powered by the Data Terminal Ready (DTR) line from the RS232 device. If these circuits don't
do the trick, the components may be desoldered and direct connection made to the DB9 pins. Pins 1 of J54 and J59 are
received data going to the GA144
pins
are transmit from the GA144, and pins
are incoming RTS. The inactive state
of each of these RS232 lines is low.
7.4.2
General-Purpose LEDs
Located between the two DB9 patterns are four general-purpose LEDs, which may be turned on by
supplying them with 1.8 volts on the geometrically corresponding pin of the adjacent pattern J57.
7.4.3
VGA Connector
A pattern for a female 15-pin D shell provides the means for driving a
VGA display directly from the GA144. Terminating resistor networks
must be added if the device requires them.
7.4.4
USB Connector
To facilitate development of USB device hardware and software, provision is made for attaching a
USB type B receptacle to the prototyping area.
Some interface circuitry will probably be needed.
7.4.5
RJ48 Connector
For development of 10baseT and perhaps other Ethernet interfaces, a
pattern is provided for an RJ48 receptacle. Like USB, we expect that
some minimal interface circuitry will be required as well.
7.4.6
Audio Connectors
For analog audio input/output development, up to three 3.5mm stereo TRS receptacles may be
soldered to patterns provided on the prototyping area.
7.4.7
SMA RF Connectors
At higher frequencies, RF connectors are more suitable
for carrying signals on and off the evaluation board.
Accordingly we provide five hole patterns for mounting
SMA connectors, chosen for their small size and ready
availability.






��DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
16

7.5
include small boards
which can connect various surface mount parts
to our prototyping area using 0.1" headers.
This is considerably simpler and more likely to
succeed than is "dead bugging" SMT
components.
As another example, by soldering double row
female headers appropriately in the
prototyping area, PC-104 boards may be
connected to the evaluation board. For
example, see
WinSystems® Products
which
include prototyping boards that could simply
enlarge the prototyping area, or peripheral
boards that could be used with level shifters.
Here is one possible placement of a 16-bit PC-104 connector and two views of a PC-104 board mounted on it:







�� DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
17

Physical
Documentation
This section includes signal tables, schematics and PCB layout artwork.
8.1
Bill of Materials
RefDes
Value
Type
PinsQtyManufacturerSupplierSup Part No.
22uf-25VCAP_0805
21SANYO
Caps Plus25TQC22MV
C4,C13,C20
4.7uf
CAP_0603
23
Digi-Key490-5421-1-ND
C5 (for 0.1.1 layout only)0.22uf 10% 630vCAP_0805
21
Mouser81-GRM55DR72J224KW01
C6 (for 0.1.1 layout only)0.47uf 50v 10%CAP_0805
21
Digi-Key399-3752-1-ND
470pf 5vCAP_0402
21
Digi-KeyPCC471BQCT-ND
C8 (for 0.1.1 layout only)330pf 1Kv 5%CAP_0805
21
Mouser598-MC22FF331J-F
C9,C10,C16,C21,C23,C27
CAP_0402
26
Digi-Key478-1114-1-ND
C15
68uf-16VCAP_0805
21SANYO
Caps Plus16TQC68M
C2,C3,C11,C12,C14,C17-
C19,C22,C24-C26,C28-C35
0.1uF
CAP_0402
Amer Tech Ceramics
ATCATC530L104KT16T
D1,D3,D5,D6,D8
1N3016
25On SemiconductorDigi-KeyMBRA340T3GOSCT-ND
FB1,FB2,FB3
Ferrite Bead
23
Digi-Key490-5247-1-ND
TERMBLK10
Digi-KeyED2616-ND
PJ-002B
31
Digi-KeyCP-002BH-ND
J3,J9,J18
USB
63Adam TechMouser737-USB-B-S-RA
J10,J11,J14-J16,J25,J39
CON3
37Break up 1x40Digi-KeyA26513-03-ND
J20,J29,J37
HEADER_2X2
43Break up 2x40Digi-KeyA34977-02-ND
J22
HEADER_2X3
61Break up 2x40Digi-KeyA34977-03-ND
J26,J34,J35
HEADER_1X2
23Break up 1x40Digi-KeyA26513-02-ND
J23
HEADER 2X6
1Break up 2x40Digi-KeyA34977-06-ND
J38 plus J40
HEADER 2X5
1Break up 2x40Digi-KeyA34977-05-ND
JP1
SD Connector
1GCT
Newark69R4862
K1,K2
C1-RSTSWITCH_PB
21
Digi-KeyP10877S-ND
3.3uH
Inductor
21COILCRAFTCoilcraftMSS1048-332NLC
Q1,Q2
Dual 50v N-FET
62Diodes, Inc.Digi-KeyDMN5L06DMKDICT-ND
15K 10%RES_0603
21PanasonicDigi-KeyP15KGCT-ND
RES_0603
21PanasonicDigi-KeyP100KGCT-ND
127K 1%RES_0603
21PanasonicDigi-KeyP127KHCT-ND
18.2K 1%RES_0603
21PanasonicDigi-KeyP18.2KHCT-ND
68.1K 10%RES_0603
21PanasonicDigi-KeyP68.1KHCT-ND
R12,R15
RES_0603
22PanasonicDigi-KeyP10KGCT-ND
R13,R14,R16,R17
RES_0603
24PanasonicDigi-KeyP1.0KGCT-ND
R18,R19,R20,R21,R28,R295.1K
RES_0603
26PanasonicDigi-KeyP5.1KGCT-ND
R22,R30
470 1/2WRES_1206
22Vishay/DaleDigi-Key541-470UACT-ND
R23,R31
2.7K 1/4WRES_0805
22PanasonicDigi-KeyP2.7KADCT-ND
U1,U3,U4
USB SerialFT232RQ
3FTDI
Digi-Key768-1008-1-ND
U2
RegulatorLT3480
1Linear TechnologyDigi-KeyLT3480EMSE#PBF-ND
U5,U8
MulticomputerGA144
2GreenArraysGreenArraysG144A12
SRAM
CY62167EV18LL-55
1Cypress
AvnetCY62167EV18LL-55BVXI
SPI FlashSST25WF080
81Microchip
MicrochipSST25WF080-75-4I-SAF
Quad OR74LVC32 QFN
Digi-Key568-3017-1-ND
U10
Quad NAND74LVC00 QFN
Mouser771-LVC00ABQ115
U11-U16
Octal LevelshiftTXB0108E
6Texas InstrumentsMouser595-TXB0108RGYR
TOTAL ASSEMBLED
2pin Jumpers
Jameco ValueproJameco
J52,J58
DB9F
91TE ConnectivityMouser571-5747844-4
J71
USB "B" female
61Adam TechMouser737-USB-B-S-RA
J69
RJ48 Ethernet
81TYCO
Digi-KeyA31442-ND
J62,J63,J64
3.5mm Phone Jack43KOBICONNMouser161-4033-E
Clip leads
2Circuit SpecialistsCircuitSpec
USB Cable
Monoprice
LED green 565nm T1 3/4
Jameco
Res CF 47ohm 1/4w 5%
Jameco
HEADER 2X40
Jameco
HEADER 1X40
Jameco
2GB
MMC DV Flash
1Kingston
Price Angels
TOTAL IN BAG
��DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
18

8.2
GA144 Signal map
These tables identify header pins or holes at which each chip's signals may be found.
8.2.1
Host Chip
Type

Name

Pin

Access

Description

SRAM Data
Bus

d00

1

D00

Bits 0 through 17 of node 007 UP port.

General purpose bidirectional parallel bus.


Bits 0 through 15 are connected to the SRAM BGA and probe access is not
supported except for bit 0
to probe timing
.

Mapping to SRAM data lines is
randomized for best layout.


Bits 16 and 17 are pulled down so that they will read as zero.

d01

2

None

d02

3

d03

8

d04

9

d05

10

d06

11

d07

12

d08

13

d09

16

d10

21

d11

22

d12

23

d13

24

d14

25

d15

30

d16

31

R14

d17

32

R13

GPIO

008.17

33

None

General purpose 4
-
pin node used for SRAM control (1,3
) and high order
address lines (5,17). Pins 1 and 3 are pulled up
so that the SRAM is made
inactive when chip is reset.

008.5

34

008.3

35

WE
-

008.1

36

CE
-

SRAM
Address Bus

a17

37

None

Bits 17 through 0 of node 009 UP port.

General purpose
bidirectional parallel bus.


Bits 0 through 17 are connected to the SRAM BGA and probe access is not
supported except for bit 0 to probe timing. Mapping to the low order
17
SRAM
address
lines is randomized for best layout.

A17 must be mapped
directly so
that the layout will accommodate chips with 128k or fewer words.

a16

38

a15

39

a14

42

a13

43

a12

44

a11

45

a10

46

a09

53

a08

54

a07

55

a06

56

a05

57

a04

58

a03

65

a02

66

a01

67

a00

68

A00

�� DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
19

SERDES

001.17

27

J75

Node 001 Clock

Available at dedicated SMA connector hole patterns.
.

001.1

26

J74

Node 001 Data

SERDES

701.17

86

S17

Node 701 Clock

Connected to Target node
001

SERDES. Both chips reset to
SDERDES boot.

701.1

87

S1

Node 701 Data

GPIO

300.17

14

J35.1

Sync clock

General purpose 2
-
pin node. ROM supports synchronous boot
.
May be connected to Target node 300.

300.1

15

J34.1

Sync data

GPIO

708.17

78

J23.2

Rx Input

General purpose 2
-
pin node.

ROM supports asynchronous
boot. May be connected to USB port A for IDE operations.

708.1

79

J23.4

Tx Out

GPIO

705.17

85

DI

Data In

General purpose 4
-
pin node. Normally used for boot and/or
read/write on SPI Flash and/or mass storage such as MMC

depending on jumpers. May also be free for application use
.

When MMC selected, SS
-

and other signals are on J40.

705.5

84

DO

Data Out

705.3

81

SS
-

Chip Enable
-

705.1

80

SCK

Clock

GPIO

100.17

20

J23.8

1
-
pin GPIO nodes. May be connected to USB
port B for use with high level
Virtual Machines.

200.17

18

J23.6

500.17

7

J22.1

1
-
pin GPIO node. May be used to reset the Target chip.

600.17

6

J39.1

1
-
pin GPIO node. May be used in selecting expanded SPI bus.

317.17

52

J21.5

1
-
pin GPIO nodes.
Available for application use.

417.17

59

J21.
4

Analog In

709.ai

76

J27.3

Analog nodes whose I/O is powered by separate V
DD
A bus.

A
vailable for
application use.

Analog Out

709.ao

77

J27.2

Analog In

713.ai

73

J27.4

Analog Out

713.ao

72

J27.5

Analog In

717.ai

69

J27.8

Analog Out

717.ao

70

J27
.7

GPIO

715.17

71

J27.
6

General purpose 1
-
pin node whose pin is shared (read only) by the above
analog nodes and may be used by them for timing or other purposes.

Analog In

617.ai

61

J21.2

Analog node
whose I/O is powered by V
DD
I bus.

Analog Out

617.ao

63

J21.1

GPIO

517.17

60

J21.3

General purpose 1
-
pin node whose pin is shared (read only) by Analog 617.

Analog In

117.ai

48

J21.8

Analog node whose I/O is powered by V
DD
I bus.

Analog Out

117.ao

50

J21.7

GPIO

217.17

51

J21.6

General purpose 1
-
pin node whose pin is shared (read only) by Analog 117.

Input

RESET
-

88

J20.1

Reset signal, active low.

Also pin J20.2.

Power

V
DD
C

5

J10.2

Core power bus. Powers F18A computers, and parts of I/O circuitry
(such as
registers) that are internal to them.

17

29

41

49

62

75

83

Power

V
DD
I

4

J11.2

I/O power bus. Powers I/O pads including the parts of the I/O circuitry
collocated with the pads. Includes analog pads for nodes
117 and 617.

19

28

40

47

64

82

Power

V
DD
A

74

J11.2

Analog power bus for pads of nodes 709, 713 and 717.

Ground

GND

DAP

any gnd

Common ground and heat sink.

��DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
20

8.2.2
Target Chip
Type

Name

Pin

Access

Description

Bus I/O

d00

1

J30.1

Bits 0 through 17 of node 007 UP port.


General purpose bidirectional parallel bus, such as external memory data.

d01

2

J30.2

d02

3

J30.3

d03

8

J30.6

d04

9

J30.7

d05

10

J30.8

d06

11

J30.9

d07

12

J30.10

d08

13

J30.11

d09

16

J30.12

d10

21

J30.15

d11

22

J30.16

d12

23

J31.1

d13

24

J31.2

d14

25

J31.3

d15

30

J31.4

d16

31

J31.5

d17

32

J31.6

GPIO

008.17

33

J31.7

General purpose 4
-
pin node.

Might be used for memory or bus control and handshake lines.

008.5

34

J31.8

008.3

35

J31.9

008.1

36

J31.10

Bus I/O

a17

37

J31.11

Bits 17 through 0 of node 009 UP port.


General purpose bidirectional parallel bus, such as external memory address.

a16

38

J31.12

a15

39

J31.13

a14

42

J31.14

a13

43

J31.15

a12

44

J31.16

a11

45

J36.15

a10

46

J36.14

a09

53

J36.9

a08

54

J36.8

a07

55

J36.7

a06

56

J36.6

a05

57

J36.5

a04

58

J36.4

a03

65

J32.
15

a02

66

J32.
14

a01

67

J32.
13

a00

68

J32.
12

SERDES

001.17

27

S17

Node 001 Clock

Connected to Host node 701 SERDES. Both chips reset to
SDERDES boot.

001.1

26

S1

Node 001 Data

SERDES

701.17

86

J28.2

Node 701 Clock

Available for experimentation.

701.1

87

J28.4

Node 701 Data

GPIO

300.17

14

J35.2

Sync clock

General purpose 2
-
pin
node. ROM supports synchronous boot.
May be connected to Host node 300.

300.1

15

J34.2

Sync data

�� DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
21

GPIO

708.17

78

J23.10

Rx Input

General purpose 2
-
pin node. ROM supports asynchronous
boot. May be connected to USB port
C

for IDE operations.

708.1

79

J23.12

Tx Out

GPIO

705.17

85

J32.
1

Data In

General purpose 4
-
pin node. If 705.17 is

low on reset, ROM
will attempt SPI memory boot using signal assignments
shown, driving signals on 705.5, 3, 1, and will leave these in
output mode unless programmed otherwise.

705.5

84

J32.
2

Data Out

705.3

81

J32.
3

Chip Enable
-

705.1

80

J32.
4

Clock

GPIO

100.17

20

J30.14

General purpose 1
-
pin nodes.

No special ROM or interconnections.

200.17

18

J30.13

500.17

7

J30.5

600.17

6

J30.4

317.17

52

J36.10

417.17

59

J36.3

Analog In

709.ai

76

J32.
6

Analog nodes whose I/O is powered by
separate V
DD
A bus.

Analog Out

709.ao

77

J32.
5

Analog In

713.ai

73

J32.
7

Analog Out

713.ao

72

J32.
8

Analog In

717.ai

69

J32.
11

Analog Out

717.ao

70

J32.
10

GPIO

715.17

71

J32.
9

General purpose 1
-
pin node whose pin is shared (read only) by the
above
analog nodes and may be used by them for timing or other purposes.

Analog In

617.ai

61

J36.1

Analog node whose I/O is powered by V
DD
I bus.

Analog Out

617.ao

63

J32.
16

GPIO

517.17

60

J36.2

General purpose 1
-
pin node whose pin is shared (read only)

by Analog 617.

Analog In

117.ai

48

J36.13

Analog node whose I/O is powered by V
DD
I bus.

Analog Out

117.ao

50

J36.12

GPIO

217.17

51

J36.11

General purpose 1
-
pin node whose pin is shared (read only) by Analog 117.

Input

RESET
-

88

J22.2

Reset signal,
active low.

Also pins J22.4 and 6.

Power

V
DD
C

5

J14.2

Core power bus. Powers F18A computers, and parts of I/O circuitry (such as
registers) that are internal to them.

17

29

41

49

62

75

83

Power

V
DD
I

4

J15.2

I/O power
bus. Powers I/O pads including the parts of the I/O circuitry
collocated with the pads. Includes analog pads for nodes 117 and 617.

19

28

40

47

64

82

Power

V
DD
A

74

J16.2

Analog power bus for pads of nodes 709, 713 and 717.

Ground

GND

DAP

any gnd

Common ground and heat sink.



��DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
22

8.3
Connector Pinouts
8.3.1
Power Control Section
External Connector
Pin 1 of J1 is oriented toward the bottom edge of the
board and thus is an exception to the rule.
J1


10

Gnd

9

User

supply, J4

8

Gnd

7

User supply, J5

6

Gnd

5

User supply, J6

4

Gnd

3

External Host
P
wr

2

Gnd

1

External Target
P
wr

Single Pins
J4

User supply, J1.9

J5

User supply, J1.7

J6

User supply, J1.5

Host Power Select
J10


1

External Host Pwr

2

V
DD
C
to Host

3

Main 1.8v Bus


J11


1

External Host Pwr

2

V
DD
I and A to Host

3

Main 1.8v Bus

Target Power Select
J14


1

External Target Pwr

2

V
DD
C to Target

3

Main 1.8v Bus


J15


1

External Target Pwr

2

V
DD
I to Target

3

Main 1.8v Bus


J16


1

External Target Pwr

2

V
DD
A to Target

3

Main 1.8v Bus

8.3.2
USB Serial Interfaces
Port Data Connections to Host and Target

J23


Incoming from
Port A

1

2

Host
708.17

Outgoing to
Port A

3

4

Host 708.1

Incoming from
Port B

5

6

Host 200.17

Outgoing to
Port B

7

8

Host 100.17

Incoming from
Port C

9

10

Target 708.17

Outgoing to
Port C

11

12

Target 708.1

Port A Access
J7

FTDI 3.3v Pwr


J8


1

DTR signal

2

CBUS2

3

CBUS3

4

CBUS4

Port B Access
J12

FTDI 3.3v Pwr

J24

RTS signal


J13


1

DTR signal

2

CBUS2

3

CBUS3

4

CBUS4


�� DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
23

Port C Access
J
19

FTDI 3.3v Pwr


J17


1

DTR signal

2

CBUS2

3

CBUS3

4

CBUS4

8.3.3
Host Chip
Probe Points
CE
-

SRAM chip enable from 008.1

WE
-

SRAM write enable from 008.3

D00

SRAM data bit

A00

SRAM address bit

SS
-

Chip select for
SPI Flash chip

SCK

Clock line for SPI bus (selectively

DO

Data out bus from G144 to SPI devices

DI

Data in bus from SPI devices to G144



J2
0


Host RESET pin

1

2

Host RESET pin

USB A RTS signal

3

4

Host reset
ckt & J25.3


J
25


1

Ground

2

SPI Flash RST
-

pin

3

Host reset ckt & J20.4


J
26


1

Host 705.17

2

1K Pull
-
up to 1.8v

SPI Bus Expansion
J
39


1

Host 600.17

2

FLASHENABLE
-

3

Ground



J
37


FLASHENABLE
-

on SPI bus.

1

2

2 inputs to NAND. Output
low
enables MMC on SPI bus.

3

4

Uncommitted Host Pins
J
21


1

617.ao

2

617.ai

3

517.17

4

417.17

5

317.17

6

217.17

7

117.ao

8

117.ai


J
27


1

Ground

2

709.ao

3

709.ai

4

713.ai

5

713.ao

6

715.17

7

717.ao

8

717.ai

8.3.4
Target Chip
Probe Points
S17

SERDES Clock between Host and Target

S1

SERDES Data



J22


Host 500.17

1

2

Target RESET
-

pin

USB C RTS signal

3

4

Target reset circuit

5

6


J35


1

Host 300.17

2

Target 300.17


J34


1

Host 300.1

2

Target 300.1

��DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
24



J30


d00

1

2

d01

d02

3

4

600.17

500.17

5

6

d03

d04

7

8

d05

d06

9

10

d07

d08

11

12

d09

200.17

13

14

100.17

d10

15

16

d11



J3
1


d12

1

2

d13

d14

3

4

d15

d16

5

6

d17

008.17

7

8

008.5

008.3

9

10

008.1

a17

11

12

a16

a15

13

14

a14

a13

15

16

a12



J3
2


705.17

1

2

705.5

705.3

3

4

705.1

709.ao

5

6

709.ai

713.ai

7

8

713.ao

715.17

9

10

717.ao

717.ai

11

12

a00

a01

13

14

a02

a03

15

16

617.ao



J3
6


617.ai

1

2

517.17

417.17

3

4

a04

a05

5

6

a06

a07

7

8

a08

a09

9

10

317.17

217.17

11

12

117.ao

117.ai

13

14

a10

a11

15

16

Ground



J28


Ground

1

2

701.17 SERDES clock

3

4

701.1 SERDES data

8.3.5
Prototyping Area
SD Socket

signals

J38

J40

SPI Bus

signals

CLK/SCLK

1

1

SPI CLK MMC

DAT3/CS
-

2

2

SPI CS
-

MMC

CMD/SI

3

3

SPI DO

DAT0/SO

4

4

SPI DI

V
DD

5

5

1.8v


J33

SD Socket Signals

1

DAT1

2

DAT2

3

Card Present

4

Write Protect

TI TXB0108 Level Shifterss
Each level shifter is surrounded by this hole pattern:
A2

V
CC
A

A1

B1

V
CC
B

B2

A3





B3

A4





B4

A5





B5

A6





B6

A7

A8

OE

V
SS

B8

B7

Convenience Logic
TP4

NAND 1 Input

TP5

NAND 1 Input

TP11

NAND 1 Output

TP6

NAND
2

Input

TP7

NAND
2

Input

TP12

NAND
2

Output

TP8

NAND
3

Input

TP9

NAND
3

Input

TP13

NAND
3

Output

TP2

OR

Input

TP3

OR

Input

TP10

OR

Output

�� DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
25

DB9 RS232 site Left (J52)
J54


1

R
X

I
n
coming

2

TX Outgoing

3

RTS Incoming

Note these signals are on chip side of minimal
quasi-RS232 transceiver.
General Purpose LEDs
J57


1

V
DD

for D12

2

V
DD

for D13

3

V
DD

for D14

4

V
DD

for D15

DB9 RS232 site Right (J58)
J59


1

RX Incoming

2

TX Outgoing

3

RTS Incoming

Note these signals are on chip side of minimal
quasi-RS232 transceiver.
VGA site (J
)
J67


1

RED

2

GREEN

3

BLUE

4

HSYNC

5

VSYNC

6

gnd

USB site (J
)
J68


1

V
CC

2

D+

3

D
-

RJ48 site (J69)
J
66


1

TX+

2

TX
-

3

RX+

4

RX
-

5

n/c

Audio site (J62, 63, 64)
J65


1

RING

2

NC TIP SWITCH

3

TIP

4

SLEEVE


J60


1

RING

2

NC TIP SWITCH

3

TIP

4

SLEEVE


J61


1

RING

2

NC TIP SWITCH

3

TIP

4

SLEEVE

SMA
site (J41, 49, 51, 55)
J48


1

J41 Signal

2

Gnd


J50


1

J4
9

Signal

2

Gnd


J53


1

J
5
1 Signal

2

Gnd


J56


1

J
55

Signal


Gnd



��DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
26

8.4
Errata
Known problems at the time of this writing are as follow:
PCB REV

DESCRIPTION

FIX OR WORK
-
AROUND

0.1.1

The VGA connector hole pattern J70 is rotated 180
degrees. Ground pins are connected
inappropriately and connector is physically
impractical to use when pointed inward.

Do not use J70. The pattern and wiring will be
corrected in the next board
revision.

0.1.1

The FTDI transmit and receive LEDs are not
populated due to an error in circuit design.

Do not use.
Circuit and layout will be correct
ed in
the next board revision.

0.1.1

The general purpose LEDs (see J57) are not
populated due to an
error in circuit design.

Do not use. Circuit and connectors will be changed
in the next board revision.

8.5
Schematics
and Layout
The following nine pages may be used to print or view high resolution renderings of these graphics.
Status of artwork: These are production drawings.
�� DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11
35

Data Book Revision History
REVISION

DESCRIPTION

11072
6

Preliminary release with pre
-
production drawings
.

110926

Upgrade document status to Production reflecting board revision 0.1.1.
Added details in Power
Configuration section (3). Added table showing FTDI flash configuration (4.3).
Corrected Target pin
connections to J32 in 8.1.2 and 8.2.4.
Clarified jumper table in 8.2.2. Added Errata.
Updated schematics
and layout to Productio
n. Added Bill of Materials.
Various typos.










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Printed in the United States of America
Phone (775) 298-4748 fax (775) 548-8547 email [email protected]
Copyright
©
2010
-
201
1
, GreenArrays, Incorporated


GreenArrays

Product Data Book DB003
Revised

9/26/11



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